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Machine-Level Programming I: Basics 15-213/18-213: Introduction to Computer Systems 5th Lecture, January 30, 2018 Instructors: Franz Franchetti and Seth C. Goldstein

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Office Hours Not too well attended (yet?) Ask your TAs about how it was last year… You can choose from coffee, tea, and hot chocolate Here’s where my office is: HH A312 The time: Tues. 4pm-5pm

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Today: Machine Programming I: Basics History of Intel processors and architectures Assembly Basics: Registers, operands, move Arithmetic & logical operations C, assembly, machine code

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Intel x86 Processors Dominate laptop/desktop/server market Evolutionary design Backwards compatible up until 8086, introduced in 1978 Added more features as time goes on Now 3 volumes, about 5,000 pages of documentation Complex instruction set computer (CISC) Many different instructions with many different formats But, only small subset encountered with Linux programs Hard to match performance of Reduced Instruction Set Computers (RISC) But, Intel has done just that! In terms of speed. Less so for low power.

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Intel x86 Evolution: Milestones Name Date Transistors MHz 8086 1978 29K 5-10 First 16-bit Intel processor. Basis for IBM PC & DOS 1MB address space 386 1985 275K 16-33 First 32 bit Intel processor , referred to as IA32 Added “flat addressing”, capable of running Unix Pentium 4E 2004 125M 2800-3800 First 64-bit Intel x86 processor, referred to as x86-64 Core 2 2006 291M 1060-3333 First multi-core Intel processor Core i7 2008 731M 1600-4400 Four cores (our shark machines)

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Intel x86 Processors, cont. Machine Evolution 386 1985 0.3M Pentium 1993 3.1M Pentium/MMX 1997 4.5M PentiumPro 1995 6.5M Pentium III 1999 8.2M Pentium 4 2000 42M Core 2 Duo 2006 291M Core i7 2008 731M Core i7 Skylake 2015 1.9B Added Features Instructions to support multimedia operations Instructions to enable more efficient conditional operations Transition from 32 bits to 64 bits More cores

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Intel x86 Processors, cont. Past Generations 1st Pentium Pro 1995 600 nm 1st Pentium III 1999 250 nm 1st Pentium 4 2000 180 nm 1st Core 2 Duo 2006 65 nm Recent Generations Nehalem 2008 45 nm Sandy Bridge 2011 32 nm Ivy Bridge 2012 22 nm Haswell 2013 22 nm Broadwell 2014 14 nm Skylake 2015 14 nm Kaby Lake 2016 14 nm Coffee Lake 2017? 14 nm Cannonlake 2018? 10 nm

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2018 State of the Art: Skylake (Core i7 v6) Mobile Model: Core i7 2.6-2.9 GHz 45 W Desktop Model: Core i7 Integrated graphics 2.8-4.0 GHz 35-91 W Server Model: Xeon Integrated graphics Multi-socket enabled 2-3.7 GHz 25-80 W

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x86 Clones: Advanced Micro Devices (AMD) Historically AMD has followed just behind Intel A little bit slower, a lot cheaper Then Recruited top circuit designers from Digital Equipment Corp. and other downward trending companies Built Opteron: tough competitor to Pentium 4 Developed x86-64, their own extension to 64 bits Recent Years Intel got its act together Leads the world in semiconductor technology AMD has fallen behind Relies on external semiconductor manufacturer

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Intel’s 64-Bit History 2001: Intel Attempts Radical Shift from IA32 to IA64 Totally different architecture (Itanium) Executes IA32 code only as legacy Performance disappointing 2003: AMD Steps in with Evolutionary Solution x86-64 (now called “AMD64”) Intel Felt Obligated to Focus on IA64 Hard to admit mistake or that AMD is better 2004: Intel Announces EM64T extension to IA32 Extended Memory 64-bit Technology Almost identical to x86-64! All but low-end x86 processors support x86-64 But, lots of code still runs in 32-bit mode

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Our Coverage IA32 The traditional x86 For 15/18-213: RIP, Summer 2015 x86-64 The standard shark> gcc hello.c shark> gcc –m64 hello.c Presentation Book covers x86-64 Web aside on IA32 We will only cover x86-64

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Today: Machine Programming I: Basics History of Intel processors and architectures Assembly Basics: Registers, operands, move Arithmetic & logical operations C, assembly, machine code

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Levels of Abstraction

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Definitions Architecture: (also ISA: instruction set architecture) The parts of a processor design that one needs to understand for writing assembly/machine code. Examples: instruction set specification, registers Microarchitecture: Implementation of the architecture Examples: cache sizes and core frequency Code Forms: Machine Code: The byte-level programs that a processor executes Assembly Code: A text representation of machine code Example ISAs: Intel: x86, IA32, Itanium, x86-64 ARM: Used in almost all mobile phones RISC V: New open-source ISA

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Assembly/Machine Code View Programmer-Visible State PC: Program counter Address of next instruction Called “RIP” (x86-64) Register file Heavily used program data Condition codes Store status information about most recent arithmetic or logical operation Used for conditional branching

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Assembly Characteristics: Data Types “Integer” data of 1, 2, 4, or 8 bytes Data values Addresses (untyped pointers) Floating point data of 4, 8, or 10 bytes (SIMD vector data types of 8, 16, 32 or 64 bytes) Code: Byte sequences encoding series of instructions No aggregate types such as arrays or structures Just contiguously allocated bytes in memory

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x86-64 Integer Registers Can reference low-order 4 bytes (also low-order 1 & 2 bytes) Not part of memory (or cache)

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Some History: IA32 Registers

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Assembly Characteristics: Operations Transfer data between memory and register Load data from memory into register Store register data into memory Perform arithmetic function on register or memory data Transfer control Unconditional jumps to/from procedures Conditional branches Indirect branches

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Moving Data Moving Data movq Source, Dest Operand Types Immediate: Constant integer data Example: $0x400, $-533 Like C constant, but prefixed with ‘$’ Encoded with 1, 2, or 4 bytes Register: One of 16 integer registers Example: %rax, %r13 But %rsp reserved for special use Others have special uses for particular instructions Memory: 8 consecutive bytes of memory at address given by register Simplest example: (%rax) Various other “addressing modes”

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movq Operand Combinations Cannot do memory-memory transfer with a single instruction

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Simple Memory Addressing Modes Normal (R) Mem[Reg[R]] Register R specifies memory address Aha! Pointer dereferencing in C movq (%rcx),%rax Displacement D(R) Mem[Reg[R]+D] Register R specifies start of memory region Constant displacement D specifies offset movq 8(%rbp),%rdx

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Example of Simple Addressing Modes

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Example of Simple Addressing Modes

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Understanding Swap()

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Understanding Swap()

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Understanding Swap()

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Understanding Swap()

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Understanding Swap()

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Understanding Swap()

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Complete Memory Addressing Modes Most General Form D(Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]+ D] D: Constant “displacement” 1, 2, or 4 bytes Rb: Base register: Any of 16 integer registers Ri: Index register: Any, except for %rsp S: Scale: 1, 2, 4, or 8 (why these numbers?) Special Cases (Rb,Ri) Mem[Reg[Rb]+Reg[Ri]] D(Rb,Ri) Mem[Reg[Rb]+Reg[Ri]+D] (Rb,Ri,S) Mem[Reg[Rb]+S*Reg[Ri]]

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Address Computation Examples

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Address Computation Examples

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Today: Machine Programming I: Basics History of Intel processors and architectures Assembly Basics: Registers, operands, move Arithmetic & logical operations C, assembly, machine code

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Address Computation Instruction leaq Src, Dst Src is address mode expression Set Dst to address denoted by expression Uses Computing addresses without a memory reference E.g., translation of p = &x[i]; Computing arithmetic expressions of the form x + k*y k = 1, 2, 4, or 8 Example

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Some Arithmetic Operations Two Operand Instructions: Format Computation addq Src,Dest Dest = Dest + Src subq Src,Dest Dest = Dest  Src imulq Src,Dest Dest = Dest * Src salq Src,Dest Dest = Dest > Src Arithmetic shrq Src,Dest Dest = Dest >> Src Logical xorq Src,Dest Dest = Dest ^ Src andq Src,Dest Dest = Dest & Src orq Src,Dest Dest = Dest | Src Watch out for argument order! Src,Dest (Warning: Intel docs use “op Dest,Src”) No distinction between signed and unsigned int (why?)

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Quiz Time! halblustig: German, literal translation: “semi-funny” but often means “not funny at all” in Austrian German Check out: quiz: day 5: Machine Basics

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Some Arithmetic Operations One Operand Instructions incq Dest Dest = Dest + 1 decq Dest Dest = Dest  1 negq Dest Dest =  Dest notq Dest Dest = ~Dest See book for more instructions

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Arithmetic Expression Example Interesting Instructions leaq: address computation salq: shift imulq: multiplication But, only used once

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Understanding Arithmetic Expression Example

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Today: Machine Programming I: Basics History of Intel processors and architectures Assembly Basics: Registers, operands, move Arithmetic & logical operations C, assembly, machine code

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Turning C into Object Code Code in files p1.c p2.c Compile with command: gcc –Og p1.c p2.c -o p Use basic optimizations (-Og) [New to recent versions of GCC] Put resulting binary in file p

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Compiling Into Assembly C Code (sum.c)

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What it really looks like .globl sumstore .type sumstore, @function sumstore: .LFB35: .cfi_startproc pushq %rbx .cfi_def_cfa_offset 16 .cfi_offset 3, -16 movq %rdx, %rbx call plus movq %rax, (%rbx) popq %rbx .cfi_def_cfa_offset 8 ret .cfi_endproc .LFE35: .size sumstore, .-sumstore

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Object Code Assembler Translates .s into .o Binary encoding of each instruction Nearly-complete image of executable code Missing linkages between code in different files Linker Resolves references between files Combines with static run-time libraries E.g., code for malloc, printf Some libraries are dynamically linked Linking occurs when program begins execution

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Machine Instruction Example C Code Store value t where designated by dest Assembly Move 8-byte value to memory Quad words in x86-64 parlance Operands: t: Register %rax dest: Register %rbx *dest: Memory M[%rbx] Object Code 3-byte instruction Stored at address 0x40059e

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Disassembling Object Code Disassembler objdump –d sum Useful tool for examining object code Analyzes bit pattern of series of instructions Produces approximate rendition of assembly code Can be run on either a.out (complete executable) or .o file

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Alternate Disassembly Within gdb Debugger Disassemble procedure gdb sum disassemble sumstore

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Alternate Disassembly Within gdb Debugger Disassemble procedure gdb sum disassemble sumstore Examine the 14 bytes starting at sumstore x/14xb sumstore

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What Can be Disassembled? Anything that can be interpreted as executable code Disassembler examines bytes and reconstructs assembly source

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Machine Programming I: Summary History of Intel processors and architectures Evolutionary design leads to many quirks and artifacts C, assembly, machine code New forms of visible state: program counter, registers, ... Compiler must transform statements, expressions, procedures into low-level instruction sequences Assembly Basics: Registers, operands, move The x86-64 move instructions cover wide range of data movement forms Arithmetic C compiler will figure out different instruction combinations to carry out computation