🗊Презентация Changes to LPDIMM Rev 02

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Changes to LPDIMM Rev 02, слайд №1Changes to LPDIMM Rev 02, слайд №2Changes to LPDIMM Rev 02, слайд №3Changes to LPDIMM Rev 02, слайд №4Changes to LPDIMM Rev 02, слайд №5Changes to LPDIMM Rev 02, слайд №6Changes to LPDIMM Rev 02, слайд №7Changes to LPDIMM Rev 02, слайд №8Changes to LPDIMM Rev 02, слайд №9Changes to LPDIMM Rev 02, слайд №10Changes to LPDIMM Rev 02, слайд №11Changes to LPDIMM Rev 02, слайд №12Changes to LPDIMM Rev 02, слайд №13Changes to LPDIMM Rev 02, слайд №14Changes to LPDIMM Rev 02, слайд №15Changes to LPDIMM Rev 02, слайд №16Changes to LPDIMM Rev 02, слайд №17Changes to LPDIMM Rev 02, слайд №18Changes to LPDIMM Rev 02, слайд №19
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Слайд 1


Changes to LPDIMM Rev 02
Описание слайда:
Changes to LPDIMM Rev 02

Слайд 2


1. general A. Please fix all dangling via and where possible fix Antena via (47 Dangling, 620 Antena). – one dangling line left B. clean unneeded shapes. C. move vias in all design so they will not be on shape’s edge (example in section 6)
Описание слайда:
1. general A. Please fix all dangling via and where possible fix Antena via (47 Dangling, 620 Antena). – one dangling line left B. clean unneeded shapes. C. move vias in all design so they will not be on shape’s edge (example in section 6)

Слайд 3


2. Component: nets in all design Please fix all places where nets are routed too close (touching) in voids of the reference plane above it or beneath. In the pic at following page, there is example of this case in L3 routing, with reference in L2_GND. It is wanted that lines will be far from these voids 1W (one signal width), but at least not touching if 1W is not possible.
Описание слайда:
2. Component: nets in all design Please fix all places where nets are routed too close (touching) in voids of the reference plane above it or beneath. In the pic at following page, there is example of this case in L3 routing, with reference in L2_GND. It is wanted that lines will be far from these voids 1W (one signal width), but at least not touching if 1W is not possible.

Слайд 4


2. Component: nets in all design(cont.)
Описание слайда:
2. Component: nets in all design(cont.)

Слайд 5


3. Component: Q2 Please cover pads with planes.
Описание слайда:
3. Component: Q2 Please cover pads with planes.

Слайд 6


4. Component: U9 Please enlarge VCC_1V1_VDD_S3 net all the way till route Keepin.
Описание слайда:
4. Component: U9 Please enlarge VCC_1V1_VDD_S3 net all the way till route Keepin.

Слайд 7


5. New MASK for VIA_FILL Please prepare new mask called VIA_FILL. This mask will contain all vias only in the DRAM BGA TOP layer.
Описание слайда:
5. New MASK for VIA_FILL Please prepare new mask called VIA_FILL. This mask will contain all vias only in the DRAM BGA TOP layer.

Слайд 8


6. Top layer Remove piece from top layer next to key.
Описание слайда:
6. Top layer Remove piece from top layer next to key.

Слайд 9


7. Layer 6 Increase the 1.1V plane on layer6 according to below.
Описание слайда:
7. Layer 6 Increase the 1.1V plane on layer6 according to below.

Слайд 10


8. Add via Add 1.8V via between L5 and bottom next to (672.000 -130.000)
Описание слайда:
8. Add via Add 1.8V via between L5 and bottom next to (672.000 -130.000)

Слайд 11


9. Component Q2, R36 Define R36 pad with solder mask and leave C_VDDQX_VR_CSP plane open from SM.
Описание слайда:
9. Component Q2, R36 Define R36 pad with solder mask and leave C_VDDQX_VR_CSP plane open from SM.

Слайд 12


10. Turn CSP and CSN pins in U9 to nets. Pin #8 in U9 us connected to C_VDDQX_VR_CSP plane with a small shape in the bottom. Convert the connection to normal trace and not a plane with 1 via. The same for pin #7 (VCC_0V6_VDDQX plane)
Описание слайда:
10. Turn CSP and CSN pins in U9 to nets. Pin #8 in U9 us connected to C_VDDQX_VR_CSP plane with a small shape in the bottom. Convert the connection to normal trace and not a plane with 1 via. The same for pin #7 (VCC_0V6_VDDQX plane)

Слайд 13


11. Enlarge VDDQ_DRAM rail. Rotate C102 90 degrees down (remove 1.8V via and move the GND vias). Enlarge VCC_1V1_0V6_VDDQ_DRAM plane so the vias connected to it from resistor R41 will be inside the plain and not on the edge.
Описание слайда:
11. Enlarge VDDQ_DRAM rail. Rotate C102 90 degrees down (remove 1.8V via and move the GND vias). Enlarge VCC_1V1_0V6_VDDQ_DRAM plane so the vias connected to it from resistor R41 will be inside the plain and not on the edge.

Слайд 14


12. 1.1V vias near R40 If possible, add more vias of 1.1V near R40
Описание слайда:
12. 1.1V vias near R40 If possible, add more vias of 1.1V near R40

Слайд 15


13. 1.1V/VPP TP Route a trace from DRAM to 1.1V and VPP TP instead of direct connection to the plane. If impossible, try at least to do that for 1.1V (TP11 and TP15)
Описание слайда:
13. 1.1V/VPP TP Route a trace from DRAM to 1.1V and VPP TP instead of direct connection to the plane. If impossible, try at least to do that for 1.1V (TP11 and TP15)

Слайд 16


14. Silk - TOP Fix REFDES for new components. And old components that moved. Fix silk of TP that moved. Change card name (LPDIMM_LP4_200B) to: LP4/x_200B (CNL U)
Описание слайда:
14. Silk - TOP Fix REFDES for new components. And old components that moved. Fix silk of TP that moved. Change card name (LPDIMM_LP4_200B) to: LP4/x_200B (CNL U)

Слайд 17


15. Silk - BOTTOM Change PCB PN to: J24748-001 (leave Rev 01). Change ASSY PN to: J24748-100
Описание слайда:
15. Silk - BOTTOM Change PCB PN to: J24748-001 (leave Rev 01). Change ASSY PN to: J24748-100

Слайд 18


16. New placement The next slide shows basic placement. Please move: TP17, TP18, J6, R27. Please move J5 (4 pin header) a little to the right. Place new components in the red square area. It doesn’t have to be exactly like I requested. It can be changed a little bit as long as everything fit.
Описание слайда:
16. New placement The next slide shows basic placement. Please move: TP17, TP18, J6, R27. Please move J5 (4 pin header) a little to the right. Place new components in the red square area. It doesn’t have to be exactly like I requested. It can be changed a little bit as long as everything fit.

Слайд 19


16. New placements (cont.)
Описание слайда:
16. New placements (cont.)

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