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EE 201A (Starting 2005, called EE 201B) Modeling and Optimization for VLSI Layout

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Chapter 7 Interconnect Delay 7.1 Elmore Delay 7.2 High-order model and moment matching 7.3 Stage delay calculation

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Basic Circuit Analysis Techniques Output response Basic waveforms Step input Pulse input Impulse Input Use simple input waveforms to understand the impact of network design

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Basic Input Waveforms

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Step Response vs. Impulse Response Definitions: (unit) step input u(t) (unit) step response g(t) (unit) impulse input (t) (unit) impulse response h(t) Relationship Elmore delay

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Analysis of Simple RC Circuit

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Analysis of Simple RC Circuit

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Delays of Simple RC Circuit v(t) = v0(1 - e-t/RC) under step input v0u(t) v(t)=0.9v0  t = 2.3RC v(t)=0.5v0  t = 0.7RC Commonly used metric TD = RC (Elmore delay to be defined later)

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Lumped Capacitance Delay Model R = driver resistance C = total interconnect capacitance + loading capacitance Sink Delay: td = R·C 50% delay under step input = 0.7RC Valid when driver resistance >> interconnect resistance All sinks have equal delay

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Lumped RC Delay Model Minimize delay  minimize wire length

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Delay of Distributed RC Lines

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Delay of Distributed RC Lines (cont’d)

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Distributed Interconnect Models Distributed RC circuit model L,T or  circuits Distributed RCL circuit model Tree of transmission lines

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Distributed RC Circuit Models

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Distributed RLC Circuit Model (without mutual inductance)

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Delays of Complex Circuits under Unit Step Input Circuits with monotonic response Easy to define delay & rise/fall time Commonly used definitions Delay T50% = time to reach half-value, v(T50%) = 0.5Vdd Rise/fall time TR = 1/v’(T50%) where v’(t): rate of change of v(t) w.r.t. t Or rise time = time from 10% to 90% of final value Problem: lack of general analytical formula for T50% & TR!

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Delays of Complex Circuits under Unit Step Input (cont’d) Circuits with non-monotonic response Much more difficult to define delay & rise/fall time

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Elmore Delay for Monotonic Responses Assumptions: Unit step input Monotone output response Basic idea: use of mean of v’(t) to approximate median of v’(t)

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Elmore Delay for Monotonic Responses T50%: median of v’(t), since Elmore delay TD = mean of v’(t)

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Why Elmore Delay? Elmore delay is easier to compute analytically in most cases Elmore’s insight [Elmore, J. App. Phy 1948] Verified later on by many other researchers, e.g. Elmore delay for RC trees [Penfield-Rubinstein, DAC’81] Elmore delay for RC networks with ramp input [Chan, T-CAS’86] ..... For RC trees: [Krauter-Tatuianu-Willis-Pileggi, DAC’95] T50%  TD Note: Elmore delay is not 50% value delay in general!

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Elmore Delay for RC Trees Definition h(t) = impulse response TD = mean of h(t) =

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Elmore Delay of a RC Tree [Rubinstein-Penfield-Horowitz, T-CAD’83]

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Elmore Delay in a RC Tree (cont’d)

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Elmore Delay in a RC Tree (cont’d) We shall show later on that i.e. 1-vi(T) goes to 0 at a much faster rate than 1/T when T Let

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Some Definitions For Signal Bound Computation

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Signal Bounds in RC Trees Theorem

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Delay Bounds in RC Trees

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Computation of Elmore Delay & Delay Bounds in RC Trees Let C(Tk) be total capacitance of subtree rooted at k Elmore delay

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Comments on Elmore Delay Model Advantages Simple closed-form expression Useful for interconnect optimization Upper bound of 50% delay [Gupta et al., DAC’95, TCAD’97] Actual delay asymptotically approaches Elmore delay as input signal rise time increases High fidelity [Boese et al., ICCD’93],[Cong-He, TODAES’96] Good solutions under Elmore delay are good solutions under actual (SPICE) delay

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Comments on Elmore Delay Model

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Chapter 7.2 Higher-order Delay Model

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Time Moments of Impulse Response h(t) Definition of moments

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Pade Approximation H(s) can be modeled by Pade approximation of type (p/q): where q < p

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General Moment Matching Technique Basic idea: match the moments m-(2q-r), …, m-1, m0, m1, …, mr-1

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Compute Residues & Poles

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Basic Steps for Moment Matching Step 1: Compute 2q moments m-1, m0, m1, …, m(2q-2) of H(s) Step 2: Solve 2q non-linear equations of EQ1 to get

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Components of Moment Matching Model Moment computation Iterative DC analysis on transformed equivalent DC circuit Recursive computation based on tree traversal Incremental moment computation Moment matching methods Asymptotic Waveform Evaluation (AWE) [Pillage-Rohrer, TCAD’90] 2-pole method [Horowitz, 1984] [Gao-Zhou, ISCAS’93]... Moment calculation will be provided as an OPTIONAL reading

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Chapter 7 Interconnect Delay 7.1 Elmore Delay 7.2 High-order model and moment matching 7.3 Stage delay calculation

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Stage Delay

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Modeling of Capacitive Load First-order approximation: the driver sees the total capacitance of wires and sinks Problem: Ignore shielding effect of resistance  pessimistic approximation as driving point admittance Transform interconnect circuit into a -model [O’Brian-Savarino, ICCAD’89] Problem: cannot be easily used with most device models Compute effective capacitance from -model [Qian-Pullela-Pileggi, TCAD’94]

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-Model [O’Brian-Savarino, ICCAD’89] Moment matching again! Consider the first three moments of driving point admittance (moments of response current caused by an applied unit impulse) Current in the downstream of node k

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Driving-Point Admittance Approximations Driving-point admittance = Sum of voltage moment-weighted subtree capacitance Approximation of the driving point admittance at the driver

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Driving-Point Admittance Approximations First order approximation: y(1) = sum of subtree capacitance Second order approximation: yk(2) = sum of subtree capacitance weighted by Elmore delay

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Third Order Approximation:  Model

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Current Moment Computation Similar to the voltage moment computation Iterative tree traversal: O(n) run-time, O(n) storage Bottom-up tree traversal: O(n) run-time Can achieve O(k) storage if we impose order of traversal, k = max degree of a node O’Brian and Savarino used bottom-up tree traversal

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Bottom-Up Moment Computation Maintain transfer function Hv~w(s) for sink w in subtree Tv, and moment-weighted capacitance of subtree:

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Current Moment Computation Rule #1

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Current Moment Computation Rule #2

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Current Moment Computation Rule #3

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Current Moment Computation Rule #4 (Merging of Sub-trees)

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Example: Uniform Distributed RC Segment

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Why Effective Capacitance Model? The -model is incompatible with existing empirical device models Mapping of 4D empirical data is not practical from a storage or run-time point of view Convert from a -model to an effective capacitance model for compatibility Equate the average current in the -load and the Ceff load

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Equating Average Currents

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Waveform Approximation for Vout(t) Quadratic from initial voltage (Vi = VDD for falling waveform) to 20% point, linear to the 50% point Voltage waveform and first derivative are continuous at tx

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Average Currents in Capacitors Average current of C1 is not quite as simple: Current due to quadratic current in C2 Current due to linear current in C2

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Average Currents in C1 Average current for (0,tx) in C2 Average current for (tx,tD) in C2 Average current for (0,tD) in C2

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Computation of Effective Capacitance Equating average currents Problem: tD and tx are not known a priori Solution: iterative computation Set the load capacitance equal to total capacitance Use table-lookup or K-factor equations to obtain tD and tx Equate average currents and calculate effective capacitance Set load capacitance equal to effective capacitance and iterate

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Stage Delay Computation Calculate output waveform at gate Using Ceff model to model interconnect Use the output waveform at gate as the input waveform for interconnect tree load Apply interconnect reduced-order modeling technique to obtain output waveform at receiver pins