🗊Презентация Message signaled interrupts

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Message signaled interrupts, слайд №1Message signaled interrupts, слайд №2Message signaled interrupts, слайд №3Message signaled interrupts, слайд №4Message signaled interrupts, слайд №5Message signaled interrupts, слайд №6Message signaled interrupts, слайд №7Message signaled interrupts, слайд №8Message signaled interrupts, слайд №9Message signaled interrupts, слайд №10Message signaled interrupts, слайд №11Message signaled interrupts, слайд №12Message signaled interrupts, слайд №13Message signaled interrupts, слайд №14
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Слайд 1


Message Signaled Interrupts A look at our network controller’s optional capability to utilize Message Signaled Interrupts
Описание слайда:
Message Signaled Interrupts A look at our network controller’s optional capability to utilize Message Signaled Interrupts

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The ‘old’ way In order to appreciate the benefits of using Message Signaled Interrupts, let’s first see how devices do interrupts in a legacy PC
Описание слайда:
The ‘old’ way In order to appreciate the benefits of using Message Signaled Interrupts, let’s first see how devices do interrupts in a legacy PC

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Multi-step communication A device signals that it needs CPU service The Interrupt Controller signals the CPU The CPU responds with two INTA cycles First INTA causes bit-changes in IRR and ISR Second INTA puts ID-number on system bus CPU uses ID-number to lookup IVT entry CPU saves minimum context on its stack, adjusts eflags, and jumps to specified ISR
Описание слайда:
Multi-step communication A device signals that it needs CPU service The Interrupt Controller signals the CPU The CPU responds with two INTA cycles First INTA causes bit-changes in IRR and ISR Second INTA puts ID-number on system bus CPU uses ID-number to lookup IVT entry CPU saves minimum context on its stack, adjusts eflags, and jumps to specified ISR

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Faster, cheaper, and more Faster response to interrupts is possible if the old multi-step communication scheme can be replaced by a single-step protocol Less expensive PCs can be manufactured if their total number of signal pins and the physical interconnections can be reduced More devices can have their own ‘private’ interrupt(s) if signal lines aren’t required
Описание слайда:
Faster, cheaper, and more Faster response to interrupts is possible if the old multi-step communication scheme can be replaced by a single-step protocol Less expensive PCs can be manufactured if their total number of signal pins and the physical interconnections can be reduced More devices can have their own ‘private’ interrupt(s) if signal lines aren’t required

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The ‘new’ way Message Signaling allows all the needed information to arrive in a single package, and go directly from a device to the CPU
Описание слайда:
The ‘new’ way Message Signaling allows all the needed information to arrive in a single package, and go directly from a device to the CPU

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Implementation The customary PCI Configuration Space is modified to accommodate three additional registers, which collectively are known as the MSI Capability Register Set: An MSI Control Register (16 bits) An MSI Address Register (32 bits/64 bits) An MSI Data Register (32 bits) (In fact these additions fit within a broader scheme of so-called “new capabilities”)
Описание слайда:
Implementation The customary PCI Configuration Space is modified to accommodate three additional registers, which collectively are known as the MSI Capability Register Set: An MSI Control Register (16 bits) An MSI Address Register (32 bits/64 bits) An MSI Data Register (32 bits) (In fact these additions fit within a broader scheme of so-called “new capabilities”)

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PCI Command Register
Описание слайда:
PCI Command Register

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PCI Status Register
Описание слайда:
PCI Status Register

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MSI Control Register
Описание слайда:
MSI Control Register

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MSI Address Register
Описание слайда:
MSI Address Register

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MSI Data Register
Описание слайда:
MSI Data Register

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Recall NIC’s interrupt registers
Описание слайда:
Recall NIC’s interrupt registers

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Demo module: ‘msidemo.c’ This module installs an interrupt-handler for an otherwise unused interrupt-vector It initializes the MSI Capability Registers residing in our Intel Pro1000 controller’s PCI Configuration Space, to enable the NIC to issue Message Signaled Interrupts It creates a pseudo-file (‘/proc/msidemo’) that triggers an interrupt when it’s read
Описание слайда:
Demo module: ‘msidemo.c’ This module installs an interrupt-handler for an otherwise unused interrupt-vector It initializes the MSI Capability Registers residing in our Intel Pro1000 controller’s PCI Configuration Space, to enable the NIC to issue Message Signaled Interrupts It creates a pseudo-file (‘/proc/msidemo’) that triggers an interrupt when it’s read

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Tools The ‘unused’ interrupt-number is selected by examining the settings in the IOAPIC’s Redirection Table (e.g., for serial-UART) Our NIC’s PCI Configuration Space can be viewed by installing our ‘82573.c’ module and reading its pseudo-file (‘/proc/82573’) We can watch interrupts being generated with our ‘smpwatch’ application-program
Описание слайда:
Tools The ‘unused’ interrupt-number is selected by examining the settings in the IOAPIC’s Redirection Table (e.g., for serial-UART) Our NIC’s PCI Configuration Space can be viewed by installing our ‘82573.c’ module and reading its pseudo-file (‘/proc/82573’) We can watch interrupts being generated with our ‘smpwatch’ application-program

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