🗊Презентация Programmable Logic and FPGA

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Слайд 1


Programmable logic and FPGA CPU Architecture
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Programmable logic and FPGA CPU Architecture

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Objectives What is a programmable logic What is an FPGA Structure Special functions Comparison and Usages Altera Cyclone II 20 FPGA Design Flow
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Objectives What is a programmable logic What is an FPGA Structure Special functions Comparison and Usages Altera Cyclone II 20 FPGA Design Flow

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Semiconductor Chips
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Semiconductor Chips

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Programmable logic An integrated circuit that can be programmed/reprogrammed with a digital logic of a curtain level. Started at late 70s and constantly growing Now available of up to approximately 700K Flip-Flops in a single chip.
Описание слайда:
Programmable logic An integrated circuit that can be programmed/reprogrammed with a digital logic of a curtain level. Started at late 70s and constantly growing Now available of up to approximately 700K Flip-Flops in a single chip.

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Advantages Short Development time Reconfigurable Saves board space Flexible to changes No need for ASIC expensive design and production Fast time to market Bugs can be fixed easily Of the shelf solutions are available
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Advantages Short Development time Reconfigurable Saves board space Flexible to changes No need for ASIC expensive design and production Fast time to market Bugs can be fixed easily Of the shelf solutions are available

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How it Began : PLA Programmable Logic Array First programmable device 2-level and-or structure One time programmable
Описание слайда:
How it Began : PLA Programmable Logic Array First programmable device 2-level and-or structure One time programmable

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SPLD - CPLD Simple Programmable logic device Single AND Level Flip-Flops and feedbacks Complex Programmable logic device Several PLDs Stacked together
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SPLD - CPLD Simple Programmable logic device Single AND Level Flip-Flops and feedbacks Complex Programmable logic device Several PLDs Stacked together

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FPGA - Field Programmable Gate Array
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FPGA - Field Programmable Gate Array

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Configuring LUT
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Configuring LUT

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Special FPGA functions Internal SRAM Embedded Multipliers and DSP blocks Embedded logic analyzer Embedded CPUs High speed I/O (~10GHz) DDR/DDRII/DDRIII SDRAM interfaces PLLs
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Special FPGA functions Internal SRAM Embedded Multipliers and DSP blocks Embedded logic analyzer Embedded CPUs High speed I/O (~10GHz) DDR/DDRII/DDRIII SDRAM interfaces PLLs

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Comparison
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Comparison

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Usages Digital designs where ASIC is not commercial Reconfigurable systems Upgradeable systems ASIC prototyping and emulation Education
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Usages Digital designs where ASIC is not commercial Reconfigurable systems Upgradeable systems ASIC prototyping and emulation Education

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Manufacturers Xilinx Altera Lattice Actel
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Manufacturers Xilinx Altera Lattice Actel

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Cyclone II - 20 18,752 LEs 52 M4K RAM blocks 240K total RAM bits 52 9x9 embedded multipliers 4 PLLs 16 Clock networks 315 user I/O pins SRAM Based volatile configuration
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Cyclone II - 20 18,752 LEs 52 M4K RAM blocks 240K total RAM bits 52 9x9 embedded multipliers 4 PLLs 16 Clock networks 315 user I/O pins SRAM Based volatile configuration

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Cyclone II Internals
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Cyclone II Internals

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Cyclone II Logic Array
Описание слайда:
Cyclone II Logic Array

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Cyclone II Logic Array Block (LAB) 16 LEs Local Interconnect LE carry chains Register chains LAB Control Signals 2 CLK 2 CLK ENA 2 ACLR 1 SCLR 1 SLOAD
Описание слайда:
Cyclone II Logic Array Block (LAB) 16 LEs Local Interconnect LE carry chains Register chains LAB Control Signals 2 CLK 2 CLK ENA 2 ACLR 1 SCLR 1 SLOAD

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Cyclone II Logic Element (LE)
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Cyclone II Logic Element (LE)

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LE in Normal Mode Suitable for general logic applications and combinational functions.
Описание слайда:
LE in Normal Mode Suitable for general logic applications and combinational functions.

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LE in Arithmetic Mode Ideal for implementing adders, counters, accumulators, and comparators.
Описание слайда:
LE in Arithmetic Mode Ideal for implementing adders, counters, accumulators, and comparators.

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Cyclone II I/O Features In/Out/Tri-state Different Voltages and I/O Standards Flip-flop option Pull-up resistors DDR interface Series resistors Bus keeper Drive strength control Slew rate control Single ended/differential
Описание слайда:
Cyclone II I/O Features In/Out/Tri-state Different Voltages and I/O Standards Flip-flop option Pull-up resistors DDR interface Series resistors Bus keeper Drive strength control Slew rate control Single ended/differential

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Cyclone II I/O Buffer
Описание слайда:
Cyclone II I/O Buffer

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Cyclone II Clocking 16 Global Clocks 4 PLLs
Описание слайда:
Cyclone II Clocking 16 Global Clocks 4 PLLs

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Cyclone II PLL 3 Outputs Clock Division Clock Multiplication Phase shift
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Cyclone II PLL 3 Outputs Clock Division Clock Multiplication Phase shift

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Memory
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Memory

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Cyclone II Memory Structure
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Cyclone II Memory Structure

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Cyclone II Multipliers 18x18 or 2 9x9 modes Up to 250MHz Performance
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Cyclone II Multipliers 18x18 or 2 9x9 modes Up to 250MHz Performance

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Delays and maximal frequency Gate delay – Delay of logic element DFF delay tco (tsu - Very small) Interconnect delay
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Delays and maximal frequency Gate delay – Delay of logic element DFF delay tco (tsu - Very small) Interconnect delay

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Design flow
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Design flow

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Design Rules
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Design Rules

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Programmable Logic and FPGA, слайд №31
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