🗊Презентация Wistron Corporation

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Agenda What is S3/S4? And what’s the benefit? S3/S4 power system and control sequence? How to implement S3/S4?? How to debug S3??
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Agenda What is S3/S4? And what’s the benefit? S3/S4 power system and control sequence? How to implement S3/S4?? How to debug S3??

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What is S3/S4 ??
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What is S3/S4 ??

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What is S3/S4 ??
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What is S3/S4 ??

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ACPI Power Management Spec. Sleeping State Definitions: Sleeping states are types of sleeping state within global sleeping state, G1
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ACPI Power Management Spec. Sleeping State Definitions: Sleeping states are types of sleeping state within global sleeping state, G1

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1. Global System State Definitions---G state 1. Global System State Definitions---G state 2. Device Power State Definitions---D state 3. Sleeping State Definitions---S state 4. Processor Power State Definitions---C state 5. Device and Processor Performance State Definition---P state
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1. Global System State Definitions---G state 1. Global System State Definitions---G state 2. Device Power State Definitions---D state 3. Sleeping State Definitions---S state 4. Processor Power State Definitions---C state 5. Device and Processor Performance State Definition---P state

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S3-STR(Suspend to RAM,休眠到内存) S3-STR(Suspend to RAM,休眠到内存) 優點:启动速度特别快,而且可以保留工作状态,同時此模式的耗电最少,速度也够快,达到最省电和无噪音的效果. 缺點:因數據保存于內存,系統不能完全斷電且很容易因为第三方驱动程序的兼容性问题使得系统无法正常进入Suspend状态.同時BIOS对ACPI的支持不完善,也会使STR功能无法使用。 S4-STD(Suspend to Disk,休眠到硬盤) 優點:启动速度較系統開機快且可以保留工作状态,同時此模式不耗電,速度也較快, 在系統完全掉電後不會丟失任何信息. 缺點:數據保存于HDD,在進入休眠狀態時需要保存桌面及所有打開文件和文檔的映像至HDD,相比S3待機速度較慢.
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S3-STR(Suspend to RAM,休眠到内存) S3-STR(Suspend to RAM,休眠到内存) 優點:启动速度特别快,而且可以保留工作状态,同時此模式的耗电最少,速度也够快,达到最省电和无噪音的效果. 缺點:因數據保存于內存,系統不能完全斷電且很容易因为第三方驱动程序的兼容性问题使得系统无法正常进入Suspend状态.同時BIOS对ACPI的支持不完善,也会使STR功能无法使用。 S4-STD(Suspend to Disk,休眠到硬盤) 優點:启动速度較系統開機快且可以保留工作状态,同時此模式不耗電,速度也較快, 在系統完全掉電後不會丟失任何信息. 缺點:數據保存于HDD,在進入休眠狀態時需要保存桌面及所有打開文件和文檔的映像至HDD,相比S3待機速度較慢.

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Stand-by动作原理 S3 Entry process: When user issue S3 event (Fn+Fx ,power button, LID switch), BIOS will issue to OS,then OS will notice all driver to execute S3 process. After OS finish standby process . BIOS will enable SWI. Then BIOS notice chipset to turn off S0 power.( keep S3 power alive). S3 Resume process: When Wake Event be issued, KBC will issue SWI to south bridge or south bridge get PME# from PCI device or south bridge get PWRBT# from power button, then south bridge will issue SLP_S3# to turn on S0 power again. Then BIOS will restore OS data from DIMM, then back to OS working mode.
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Stand-by动作原理 S3 Entry process: When user issue S3 event (Fn+Fx ,power button, LID switch), BIOS will issue to OS,then OS will notice all driver to execute S3 process. After OS finish standby process . BIOS will enable SWI. Then BIOS notice chipset to turn off S0 power.( keep S3 power alive). S3 Resume process: When Wake Event be issued, KBC will issue SWI to south bridge or south bridge get PME# from PCI device or south bridge get PWRBT# from power button, then south bridge will issue SLP_S3# to turn on S0 power again. Then BIOS will restore OS data from DIMM, then back to OS working mode.

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How to implement S3?? Check SW whether support ACPI spec. Check MRS( Marketing Requirement Spec.) support what kind of S3 wake event. -Power button,LID,BL2 -USB, WOR,WOL, Any-key wake -LAN, Card-Bus,IEEE 1394 (PCI PME#) Check VGA support D3hot or D3cold Check South Bridge Wake Up Interface Check KBC Wake Up interface Check Logic Gate design
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How to implement S3?? Check SW whether support ACPI spec. Check MRS( Marketing Requirement Spec.) support what kind of S3 wake event. -Power button,LID,BL2 -USB, WOR,WOL, Any-key wake -LAN, Card-Bus,IEEE 1394 (PCI PME#) Check VGA support D3hot or D3cold Check South Bridge Wake Up Interface Check KBC Wake Up interface Check Logic Gate design

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How to implement S3?? Wake Event Design: USB: If your system support USB S3 wake,you must provide 5V_S3 for USB power. And BIOS need to enable USB interface S3 wake event. WOR: If your system support Wake on Ring. You must support S3 power for pin17 of MDC connector. And Vendor’s driver need to support wake up function. PCI Device Wake( LAN, Card-Bus, 1394): If your system support PCI device wake event, you must provide S3 power to AUX power pin of device. And connect PME# to south bridge’s PME#.
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How to implement S3?? Wake Event Design: USB: If your system support USB S3 wake,you must provide 5V_S3 for USB power. And BIOS need to enable USB interface S3 wake event. WOR: If your system support Wake on Ring. You must support S3 power for pin17 of MDC connector. And Vendor’s driver need to support wake up function. PCI Device Wake( LAN, Card-Bus, 1394): If your system support PCI device wake event, you must provide S3 power to AUX power pin of device. And connect PME# to south bridge’s PME#.

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How to implement S3?? Discrete VGA support D3hot or D3cold: D3cold:When system enter S3 state, all power of VGA will be turn off. But you need to check VGA driver can be supported or not. D3hot: When system enter S3 state, some graphic power is still alive. It means that S3 power leakage will be increased. South Bridge Wake Up Interface: 1. Power Button( AUX power plane) 2. SWI from KBC( S5 power plane) 3. PME#, need pull high to S5 power plane or not( S3 or S5 power plane) 4. AC_IN ( S5 power plane) 5. Other S5 power plane’s GPIO, need to check their pull high power state.
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How to implement S3?? Discrete VGA support D3hot or D3cold: D3cold:When system enter S3 state, all power of VGA will be turn off. But you need to check VGA driver can be supported or not. D3hot: When system enter S3 state, some graphic power is still alive. It means that S3 power leakage will be increased. South Bridge Wake Up Interface: 1. Power Button( AUX power plane) 2. SWI from KBC( S5 power plane) 3. PME#, need pull high to S5 power plane or not( S3 or S5 power plane) 4. AC_IN ( S5 power plane) 5. Other S5 power plane’s GPIO, need to check their pull high power state.

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How to Debug S3?? Step 1: check HW S0 power off sequence. And DIMM whether enter self-refresh mode normally. Step 2: check S5/S3 power is alive, and no leakage in S0 power( 3D3V_S0,5V_S0,..) Step 3: check KBC or South bridge receive your wake signal. Step 4: check south bridge or KBC already send out power on signal. Step 5: check power on sequence. And DIMM’s timing from self-refresh mode to normal refresh mode. Step 6: Check BIOS resume debug code,already entire process. Step 7: Check system whether back to OS working mode. Step 8: Load current chipset register setting to compare with old setting.
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How to Debug S3?? Step 1: check HW S0 power off sequence. And DIMM whether enter self-refresh mode normally. Step 2: check S5/S3 power is alive, and no leakage in S0 power( 3D3V_S0,5V_S0,..) Step 3: check KBC or South bridge receive your wake signal. Step 4: check south bridge or KBC already send out power on signal. Step 5: check power on sequence. And DIMM’s timing from self-refresh mode to normal refresh mode. Step 6: Check BIOS resume debug code,already entire process. Step 7: Check system whether back to OS working mode. Step 8: Load current chipset register setting to compare with old setting.

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Thank You!
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Thank You!

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